Manufacturers of microelectronic devices are continually reducing the size and increasing the density of components in integrated circuits to increase the speed and capacity of the devices while reducing the overall size and power consumption. Memory device manufacturers, for example, seek to increase the capacity of memory devices (e.g., dynamic random access memory (DRAM) circuits) while reducing the size and/or increasing the density of the components in the devices without compromising performance.
DRAM circuits are generally manufactured by replicating millions of identical circuit elements (e.g., memory cells) on a single workpiece. A memory cell is an addressable location that can store one bit (binary digit) of data. Memory cells in DRAM circuits, for example, generally include a storage capacitor and an access field effect transistor. These components can also include a number of different features or structures (e.g., source areas, drain areas, gates, word lines, bit lines, etc.) that are fabricated on the workpiece. As memory cells shrink, however, it is becoming increasingly difficult to fabricate the cells within desired specifications, while simultaneously decreasing the size of the individual cells and increasing the cell density.
One area of particular concern in the manufacture of memory cells is providing capacitors with sufficiently high storage capacitance to maintain a charge at the desired refresh rates. Many manufacturers use three-dimensional capacitor configurations, such as stacked capacitors, to address this problem. Stacked capacitors are stacked or placed over the access transistor for a cell located in the workpiece. One common type of stacked capacitor, for example, is a double-sided container capacitor. A double-sided container capacitor is shaped like an upstanding tube or cylinder having a generally arcuate cross-section. Double-sided container capacitors are advantageous because they generally increase the storage capacitance of the memory cells, and yet reduce the depth of the container. Double-sided capacitors, however, generally require more lateral space than conventional capacitors, and this is not desirable because minimizing the lateral dimensions of the capacitors is necessary to increase circuit density and still electrically isolate the capacitor plates from the bit line contacts. As such, it is desirable to fabricate double-sided container capacitors that can be positioned extremely close together within the device (i.e., a high density of devices).
One particular process in fabricating double-sided capacitors is etching a relatively thick dielectric layer (e.g., a doped oxide layer) adjacent to a portion of the capacitor structure. The doped oxide etching process requires an etchant with a high selectivity to nitride because the lattice that holds the respective container capacitors together is generally made from a nitride. The etching process additionally requires a high selectivity to other materials (e.g., TiN and polysilicon) used to form portions of the capacitor structure.
Conventional etching processes include an etchant comprising a mixture of acetic acid and hydrofluoric acid (e.g., 30:1 ac-HF) to etch the doped oxide material. This etchant has a selectivity of about 250:1 for phosphosilicate glass (PSG) to nitride. Etching processes using this etchant, however, include several drawbacks. For example, the etch rate of PSG using this mixture is relatively slow (e.g., about 2,000 Å/minute) and can require about 6-7 minutes per workpiece. As a result, this process can impact the throughput of the fabrication process because the etching process needs to be run on a single wafer platform to minimize defects. Another drawback is that acetic acid is extremely flammable and difficult to work with because it has a very low flash point. Accordingly, manufacturing tools and processes generally require special safety features and precautions. These extra steps and equipment can significantly increase costs. Furthermore, acetic acid itself is quite expensive compared to other acidic solutions.
Another conventional etching process includes an etchant comprising 10:1 HF. This solution, which can etch PSG at about 9,000 Å/minute, can reduce the etching process time to less than 90 seconds per wafer. Etching processes using an etchant including 10:1 HF, however, also include several drawbacks. For example, the selectivity of this etchant is only about 200:1 for PSG:nitride. This selectivity may not be adequate in the manufacturing of certain devices (e.g., capacitors using low temperature nitrides to mitigate thermal budgets). Additionally, the etchant has a relatively low selectivity to polysilicon and TiN, and these materials can be negatively affected and/or damaged during the doped oxide etching process. Accordingly, there is a need to improve the etching processes used to etch doped oxides in the manufacture of microfeature devices.